The continuing popularity of portable electronic devices presents manufacturers with contrary goals. Battery capacity is dependent upon battery size and weight. Thus portable electronic devices could be made to operate a longer time between battery changes or recharging if these devices included heavier batteries with greater capacity. On the other hand, portable electronic devices would be more popular and more widely used if they were lighter. However, lighter weight translates into reduced battery capacity and reduced operating times. A large reduction in size of wireless telephones has taken place without significant reduction in operating times. While improvements in batteries have increased their capacity per unit weight, most of the improvement in operating time and reduction in device weight has come from improvements in the power consumption of the electronics. Many improvements have taken place in integrated circuit manufacture that have reduced the amount of power consumed by the electronics. Additional improvements have taken place by selective powering of portions of the electronics. To a large degree much of the advantage of selectively powering a microcontroller unit or a digital signal processor have already been realized by current state of the art devices. Thus manufacturers seek additional areas for power consumption reduction.
This additional area may be either a cache or main memory. Many portable electronic devices include substantial amounts of memory. Power savings may be gained by reducing leakage current in either nonvolatile or volatile memory in respective active and standby operating modes. Wei et al., “Design and Optimization of Low Voltage High Performance Dual Threshold CMOS Circuits,” 35th Design Automation Conference Proc., 489–494 (1998) disclose a circuit and method for reducing leakage current using a dual threshold voltage process. This dual threshold voltage, however, requires a separate process step and may slow normal circuit operation. Powell et al., “Gated-Vdd: A Circuit Technique to Reduce Leakage in Deep-Submicron Cache Memories,” Proc. Int. Symp. Low Power Electronics and Design (ISLPED), 90–95 (2000) disclose a dynamically resizable instruction (DRI) cache wherein a gated-ground nMOS transistor turns off unused portions of the instruction cache after application requirements are identified. Agarawal et al., “A Single-Vt Low-Leakage Gated-Ground Cache for Deep Submicron,” IEEE J. Solid-State Circuits, vol. 38, no. 2, 319–328 (February 2003) disclose a data retention gated-ground cache (DRG cache) that turns off the cache during standby mode to conserve power. However, significant array noise may be generated when these rows of memory cells are restored to active mode. Moreover, initial access time may be reduced while full power is restored. The process of fully powering these memory circuits typically requires much more time than that required for a memory access in the fully powered state. Thus, memory access time from a low power or standby state includes both the time required to power up the memory circuit and the normal access time. However, access times of these memories remains important, so it may not be feasible to completely shut the memory down to conserve power.